Senior Silicon Design Verification Engineer
Fresh Consulting is a design-led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate. We bring together amazing UX designers, sophisticated developers, digital strategists, and top-notch engineers to help companies create fresh experiences that connect humans, systems, and machines. We’ve been growing fast and need someone to help us continue to manage the delivery of high-quality work in a fast-paced environment.
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Title: Senior Silicon Design Verification Engineer
Duration: 1 year with high possibly of extension
Location: Remote. Must live and work in AZ or CA or IL or IN or NV or NY or OR or TX or UT or WA
Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan and much more!
Hours: Minimum 40 Hours/Week
Role:
– Develop and implement test/verification plans, methodologies and tool flows for graphics/display IPs.
– Define and implement IP/SubSystem verification plans, test benches and simulation/emulation coverage leading to fully functional IPs/SubSystems/SoCs.
– Define and implement system/integration tests.
– Work with cross functional teams to identify best verification methodology.
– Support integration of IP block tests into larger SubSystem or SoC environment tests.
– Implement testbench and scoreboards / checkers.
– Implement test sequences as per plan and debug failures.
– Achieve 100% functional, code coverage.
Skills
– 7+ years of proven experience as a DV engineer.
– Hands on experience with executable test plans and Coverage Driven verification.
– Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology).
– Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools.
– 2+ Years of experience with C/C++.
– DV (system Verilog, C/C++).
– Strong DV background (test plan development, test writing, UVM).
Preferred Skills:
– Experience in GPU, Display, or Imaging Pipeline Silicon development.
– Experience in development System Verilog UVM testbench environment from scratch.
– Experience with Software/Hardware Co-simulation (DPI/VPI).
– Experience with C/C++ modeling of the Hardware Systems.
– Experience with verification of high speed interfaces like MIPI.
– Experience with on-chip bus protocols (AXI, AXI-Lite, AHB, OCP).
– Experience with post-silicon lab/bench test/validation.
– Experience with UPF based simulation flow.
Education: BSEE, BSCSE or related or experience.
FRESH–
– Work on engineering and research assignments with F500 companies and startups.
– The relationships that we have created with our clients are one of a kind.
– We help solve problems in many technologies focusing on R&D, product development, and manufacturing.
– We work at the most cutting-edge and latest technologies from AR/VR to Autonomous technologies.
– Closely working with our clients, we believe that long term investments are extremely important to maintain the culture we together have created.
We’re a handpicked team of Engineers, digital strategist, designers, and developers united
together in creating a fresh experience. Whether we are strategizing, designing, developing, or analyzing, our integrated team works as an extension of yours to improve your impact, your usability, and your customer conversion. In the process, we collaborate with you to get to know your business, understand your industry, and incorporate your big ideas into memorable experiences that keep your customers coming back for more.
Fresh Consulting is a participating E-Verify company.
freshconsulting.com
Compensation offered will be determined by factors such as location, level, job-related knowledge, skills, and experience. Range $75hr – $120hr.