Senior Silicon Design Verification Engineer

  • Engineering
  • Onsite in Sunnyvale, CA or Los Angeles, CA or San Diego, CA.

Fresh Consulting is a design-led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate.  We bring together amazing UX designers, sophisticated developers, digital strategists, and top-notch engineers to help companies create fresh experiences that connect humans, systems, and machines.  We’ve been growing fast and need someone to help us continue to manage the delivery of high-quality work in a fast-paced environment. 
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Visit freshconsulting.com/portfolio to see our project work across several industries.
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Title: Senior Silicon Design Verification Engineer 
Duration: 1 year with high possibly of extension
Location: Onsite in Redmond, WA
Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan and much more!
Hours: Minimum 40 Hours/Week 

Onsite and proof of vaccination required.

Role:
– Responsible for low power verification including both dynamic and static verification.
– Write and augment existing testplans.
– Implement testbench and scoreboards / checkers.
– Implement test sequences as per plan and debug failures.
– Achieve 100% functional, code, and power coverage.
– Work closely with designers, micro architects & f/w to resolve issues.
– Ability to communicate & articulate clearly progress / issues with project leads.

Skills:
– 7+ years of proven experience as a DV engineer – candidate will have hands on Experience with executable test plans and Coverage Driven verification.
– Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology).
– Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools.
– Experience with UPF based simulation flow.
– 2+ Years of experience with C/C++.
– Power and performance modeling or DV (C, system C, system Verilog, or matlab).
– Strong DV background (test plan development, test writing, UVM).
– Experience with low power verification (UPF).
– Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows.

Preferred Skills:
– Power and performance FPGA validation.
– Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.
– Experience with Power Aware GLS flow.
– Tcl, Python, Perl, Shell (or similar) scripting language.
– ASIC design experience.
– Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators.
– Experience with complex SoCs.
– Knowledge of coverage merging across simulation and formal.
– Experience with low power verification.
– Knowledge with assertions (SVA) or others.
– Knowledge of digital ASICs design flows.

Education: BSEE, BSCSE or related field or equivalent experience

***Must be authorized to work with no visa transfer or sponsorship now or in the future***

FRESH–
– Work on engineering and research assignments with F500 companies and startups.   
– The relationships that we have created with our clients are one of a kind.    
– We help solve problems in many technologies focusing on R&D, product development, and manufacturing.    
– We work at the most cutting-edge and latest technologies from AR/VR to Autonomous technologies.    
– Closely working with our clients, we believe that long term investments are extremely important to maintain the culture we together have created.

We’re a handpicked team of Engineers, digital strategist, designers, and developers united 
together in creating a fresh experience. Whether we are strategizing, designing, developing, or analyzing, our integrated team works as an extension of yours to improve your impact, your usability, and your customer conversion. In the process, we collaborate with you to get to know your business, understand your industry, and incorporate your big ideas into memorable experiences that keep your customers coming back for more.

Fresh Consulting is a participating E-Verify company.

freshconsulting.com

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